Back Grinding determines the thickness of the wafer

Back Grinding determines the thickness of the wafer

2021-11-04 15:58:46 6

GRISH® Polishing Solutions for Indium Phosphide/Gallium Arsenide and other semiconductor materialsAfter the front-end process and passing the wafer test, the back-end process begins with Back Grinding. Back grinding is the process of thinning the back side of the wafer, not only to reduce the thickness of the wafer, but also to link the front-end and back-end processes to solve problems that arise between the front and back-end processes. The thinner the semiconductor chip (Chip), the more chips can be stacked (Stacking), the higher the level of integration. However, the higher the level of integration may lead to a decline in product performance. Therefore, there is a contradiction between the integration degree and the improvement of product performance. Therefore, the grinding method that determines the wafer thickness is one of the keys to reduce the cost of semiconductor chips and determine the quality of the product.

1. Purpose of Back Grinding


In the process of making a semiconductor from a wafer, the appearance of the wafer is constantly changing. First, in the wafer manufacturing process, the wafer's edge and surface are polished (Polishing), a process that typically grinds both sides of the wafer. After the front-end process, you can start to grind only the back side of the wafer back grinding process, can remove the front-end process in the chemical contamination of the part, and thin the thickness of the chip, which is very suitable for the production of IC cards or mobile devices equipped with thin chips. In addition, this process has the advantage of reducing resistance, reducing power consumption, increasing thermal conductivity and rapid heat dissipation to the back of the wafer. However, at the same time, because the wafer is thin, it is easy to be broken or warped by external forces, making the processing step more difficult.

2. Detailed process flow of Back Grinding


 Backside grinding can be specifically divided into the following three steps: first, apply protective tape lamination (Tape Lamination) on the wafer; second, grind the backside of the wafer; third, before separating the chip from the wafer, the wafer needs to be placed on the protective tape wafer patch (Wafer Mounting). The wafer mounting process is a preparatory stage for separating the chip (dicing the chip) and therefore can also be included in the dicing process. In recent years, as chips become thinner, the process sequence may change and the process steps become more and more refined.

3. Tape Lamination process to protect wafers


 The first step in backside lapping is the application of a film. This is a coating process in which tape is applied to the front side of the wafer. When backside lapping is performed, the silicon compound spreads around and the wafer may break or warp due to external forces during the process, and the larger the wafer area, the more susceptible it is to this phenomenon. Therefore, a thin Ultra Violet (UV) blue film is applied to protect the wafer before the backside is ground.

 When applying the film, the adhesion needs to be improved so that there are no gaps or bubbles between the wafer and the tape. However, after backside grinding, the tape on the wafer should be exposed to UV light to reduce the adhesion. The residue of the tape should not be left on the wafer surface after peeling. Sometimes, the process uses a non-UV reduced tack film treatment with weak adhesion and prone to air bubbles, which has many disadvantages but is inexpensive. In addition, a Bump (Bump) film, which is twice as thick as the UV reduction film, is also used and is expected to be used more and more frequently in the future.

4. Wafer thickness is inversely proportional to chip packaging


 The thickness of wafers that have been backside ground is typically reduced from 800-700㎛ to 80-70㎛. Wafers thinned to one-tenth can be stacked four to six layers. Recently, wafers can even be thinned to about 20㎛ by a twice-ground process, resulting in stacks of 16 to 32 layers, a multilayer semiconductor structure known as a multichip package (MCP). In this case, despite the use of multilayer structures, the total height of the finished package must not exceed a certain thickness, which is why thinner wafers are always sought. The thinner the wafer, the more defects there will be and the more difficult it will be to perform the next process. Therefore, advanced technology is needed to improve this problem.

5. Change of back grinding method


 Backside grinding technology continues to evolve by cutting wafers as thin as possible to overcome the limitations of processing technology. For common wafers with thicknesses greater than or equal to 50㎛, backside grinding is a three-step process: Rough Grinding, followed by Fine Grinding, and then cutting and polishing the wafer after two passes. At this point, similar to Chemical Mechanical Polishing (CMP), a slurry and deionized water are generally put between the polishing pad and the wafer. This polishing work can reduce the friction between the wafer and the polishing pad and make the surface shiny. When the wafer is thick, Super Fine Grinding (Super Fine Grinding) can be used, but the thinner the wafer, the more polishing is required.

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If the wafers become thinner, external defects tend to occur during the cutting process. Therefore, if the wafer thickness is 50㎛ µm or less, the process sequence can be changed. In this case, the scribing before thinning (DBG, Dicing Before Grinding) method is used, where the wafer is cut in half before the first grinding. The chip is safely separated from the wafer in the order of scribing (Dicing), grinding and scribing. In addition, there are special lapping methods that use a strong glass plate to prevent wafer breakage.

As the miniaturization of appliances requires more and more integration, backside lapping technology should also continue to develop not only to overcome its limitations. At the same time, it is important not only to solve the problem of wafer defects, but also to be prepared for new problems that may arise in future processes. In order to solve these problems, it may be necessary to switch the process sequence, or the introduction of chemical etching technology applied to the front-end process of the semiconductor, the overall development of new processing methods. Various exploration attempts are being made on lapping methods in order to address the defects inherent in large area wafers. In addition, research is being conducted on how to recycle the silicon dross generated after grinding wafers.


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