The development of "light, thin, short and small" semiconductor packages

The development of "light, thin, short and small" semiconductor packages

2022-05-24 13:35:37 3

Circuit-patterned wafers prepared through the semiconductor manufacturing (FAB) process are susceptible to various factors such as temperature changes, electrical shock, and chemical and physical external damage. To compensate for these weaknesses, the chip is separated from the wafer and then packaged, a method known as "packaging". As with semiconductor chips, packaging has evolved in the direction of "light, thin, short, and small". However, when connecting signals from the inside of the chip to the outside of the package, the package should not act as an obstacle. Packaging technology includes "Internal Structure", "External Structure" and "Surface Mounting Technology (SMT)". Surface Mounting Technology (SMT)".

1. Trends in packaging

 The development of new semiconductor packages must first change the way the package is mounted on the motherboard and the external form. Next, the internal structure and material of the package must be changed. When the package structure is more complex, the more pins (Pin) or solder balls (Ball) soldered on the motherboard, the smaller the pin pitch. Currently, the number of contacts between the package and the motherboard is rapidly approaching its limit and saturation point.

2. Package structure

Semiconductor packages include semiconductor chips, carriers for loading the chips (package PCBs, leadframes, etc.), and the plastisol for encapsulating these devices.

 In addition, internal and external connection paths are used to connect signals from the internal chip to the external. Whether the connection is internal or external, this connection used to be made using wires (leads or leadframes), but recently it has become common to use dots (buffer pads or solder balls). At the same time, the plastic sealant plays an important role in removing internal heat and protecting the chip from external damage.

3. Three elements that determine the type of package: internal structure, external structure and placement

 Until the late 1980s, the common way to connect the package internals was wire bonding, where gold wires were used to connect the chip pads to the carrier pads. However, as the package size decreases, the volume occupied by the metal wires inside the package also increases. To solve this problem, instead of removing the metal wires, the bumps (Bumps) are used instead of metal wires for internal connection. Of course, this does not mean that the lead bonding method is completely unusable. When using Bump Attaching, the Bump Attaching (Bump Attaching) process and Epoxy Filling (Under-Fill) method are required instead of Die-Attaching and Lead Bonding processes.

 The external connection method has also been changed from leadframes to solder balls. This is because leadframes and wires have the same disadvantages. In the past, the use of "wire - lead frame - PCB through-hole insertion", and now the most commonly used is "bump - Ball Grid Array (Ball Grid Array, abbreviated as BGA) - surface mount technology".

4. Internal package types

4.1 Pinless Semiconductor: Flip chip

 Semiconductor packages can also be divided into Wiring Type and Flip Chip Type based on their internal structure. The Wiring Type method has the chip facing upward and is connected to the carrier by lead bonding. The flip chip method, on the other hand, places the chip face down and connects a very small diameter tin ball (conductive metal called a bump) to the pad. Therefore, the flip-chip method does not require long wires to make the semiconductor chip attached to the substrate, and has the characteristics of short signal transmission distance and strong adhesion. This can be said to be an innovative technology for improving lead bonding defects.

The biggest advantage of flip-chip is its ability to reduce package size and improve power consumption and signal transmission process. It is faster due to its shorter length, which is less affected by resistance and peripheral noise. Therefore, it is also important which metal is used for the bump material. Currently the most common are solder or gold. Another key point of flip chip is which epoxy is used to fill the gap between the bump and the carrier. In addition, flip-chip does not use wires that occupy a large area and can reduce the size of the formed chip, so it is widely used in small electronic devices such as cell phones. That is, as the area of the solder pad (Footprint) encapsulated on the motherboard is reduced, it is more often used in high-density substrate technology. The emergence of small electronic devices such as smartphones has brought about a major shift in packaging technology.

4.2 Three-dimensional packaging technology that creates vertical vias between chips: Through Silicon Via (TSV)

To increase the density of the chip package, we use multilayer packages that stack multiple semiconductor chips. There are two types of multi-chip packages at the wafer level: wire bonding and silicon through-hole (TSV). TSV is a stacked chip with vertical vias drilled through the chip and connected to the signal lines through silicon feedthrough electrodes. The advantage is the fast signal transmission speed and high package density. Compared to two-dimensional packaging techniques that deal with individual chips, silicon via vias (TSV) can be considered as a three-dimensional packaging technique. If multiple layers of chips are connected with wires, a step-stack structure is formed and the area increases approximately twofold. But silicon through-hole (TSV) can form a vertical stacking structure like an apartment building, requiring only about 1.2 times the chip area. Due to the higher efficiency of space usage of silicon through-hole (TSV) technology, the application scope is gradually expanding.

5. External package type and placement method - based on the way the package is connected to the external

 There are various types of package chips. As an example, there is the leadframe type Dipping for PCB through-hole insertion, which was developed in the order of SIP1, ZIP2, DIP3 and PGA4. However, it is currently used only in certain cases due to its extremely limited ability to reduce the area occupied by the motherboard solder pad.

 Among the leadframe types there is also a small outline (Small Outline, SO) packaging technology which belongs to the surface mount technology, by bending the leads to improve integration. It has been developed to SOIC and SOJ (J-type pin small outline package) and is widely used. In addition, the Quad Flat Package (QFP) was used on CPU chips. Subsequently, the package technology changed from leadframe type to spherical, which gradually led to the derivation of Ball Contact Array (BGA). Currently, spherical has become the mainstream.

5.2 Mounting method

 Package assembly method is mainly divided into surface mount technology (SMT) and PCB through-hole insertion technology. As the name implies, surface mount technology (SMT) is to fix the chip on the surface of the motherboard through welding, while PCB through-hole insertion technology is to insert the chip pins into the corresponding mounting holes of the motherboard, and then weld with the pads of the motherboard to fix.

 However, due to the motherboard mounting holes occupy too large an area, in order to achieve a "thin and short" package, the mounting method has developed into a hole-free surface mount technology. In the leadframe method, SOO type (SOIC and SOJ) and TSOP have been developed for surface mounting from the beginning, and the BGA type ball itself is used for mounting on the motherboard, so the surface mounting method is also applicable.

As packaging technology evolves towards "thin and light", the internal and external shape of the package and the mounting method also change. Semiconductor package chips have high performance requirements in terms of power consumption, speed and environment. To meet this requirement, materials are also changing. The sequence of package changes is usually structure, material and function, but this does not apply in all cases. Package types can be divided into MCP (Multi Chip Package), SiP (System in Package), PoP (Package on Package), CSP (Chip Scale Package), etc., depending on the perspective. To avoid confusion, this article classifies the common package products from the structure level.

1SIP (Single Inline Package): Single Inline Package (SIP) is a package in which the pins are arranged in a straight line extending from one side of the package body.

1ZIP (Zig-zag Inline Package): Zig-zag Single Inline Package (ZIP) is a package in which the pins are arranged in a zig-zag pattern.

1DIP (Dual Inline Package): Dual Inline Package (DIP) is a package in which the pins are arranged in two rows.

1PGA (Pin Grid Array): Pin Grid Array Package (PGA) is a package with multiple square-shaped pins inside and outside the chip, and each square-shaped pin is arranged at a certain distance along the perimeter of the chip.


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